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SY56040AR
Low Voltage 1.2V/1.8V/2.5V CML 4x4 Crosspoint Switch 6.4Gbps, 5GHz
General Description
The SY56040AR is a fully differential, low voltage 1.2V/1.8V/2.5V CML 4x4 Crosspoint switch. The SY56040AR can process clock signals as fast as 5GHz or data patterns up to 6.4Gbps. The differential input includes Micrel's unique, 3-pin input termination architecture that interfaces to LVPECL, LVDS or CML differential signals as small as 100mV (200mVpp) without any level-shifting or termination resistor networks in the signal path. For AC-coupled input interface applications, an internal voltage reference is provided to bias the VT pin. The outputs are 400mV CML, with extremely fast rise/fall times guaranteed to be less than 80ps. The SY56040AR operates from a 2.5V 5% core supply and a 1.2V/1.8V/2.5V 5% output supply and is guaranteed over the full industrial temperature range (- 40C to +85C). The SY56040AR is part of Micrel's (R) high-speed, Precision Edge product line. Datasheets and support documentation can be found on Micrel's web site at: www.micrel.com.
Precision Edge
(R)
Features
* 1.2V/1.8V/2.5V CML 4x4 Crosspoint Switch * Guaranteed AC performance over temperature and voltage: - DC to 6.4Gbps throughput - <400ps typical propagation delay (IN-to-Q) - <25ps typical output skew - <80ps rise/fall times * Ultra-low jitter design - <1psRMS cycle-to-cycle jitter - <10psPP total jitter - <1psRMS random jitter - <10psPP deterministic jitter * High-speed CML outputs * 2.5V 5% , 1.2V/1.8V/2.5V 5% power supply operation * Industrial temperature range: -40C to +85C (R) * Available in 44-pin (7mm x 7mm) MLF package
Applications
* * * * Data Distribution: OC-48, OC-48+FEC SONET clock and data distribution Fibre Channel clock and data distribution Gigabit Ethernet clock and data distribution
Markets
* * * * * * * Storage ATE Test and measurement Enterprise networking equipment High-end servers Access Metro area network equipment
Precision Edge is a registered trademark of Micrel, Inc. MLF and MicroLeadFrame are registered trademarks of Amkor Technology. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
September 2008
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SY56040AR
Functional Block Diagram
Truth Table
Input Select Address Table SIN1 0 0 1 1 SIN0 0 1 0 1 INPUT IN0 IN1 IN2 IN3 0 0 1 1 Output Select Address Table SOUT1 SOUT0 0 1 0 1 OUTPUT Q0 Q1 Q2 Q3
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SY56040AR
Ordering Information (1)
Part Number SY56040ARMY SY56040ARMYTR
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only 2. Tape and Reel.
(2)
Package Type MLF-44 MLF-44
Operating Range Industrial Industrial
Package Marking SY56040ARMY with Pb-Free bar-line indicator SY56040ARMY with Pb-Free bar-line indicator
Lead Finish Matte-Sn Matte-Sn
Pin Configuration
44-Pin MLF (MLF-44)
(R)
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SY56040AR
Pin Description
Pin Number 17,15 10,8 4,2 41,39 16 9 3 40 18 19 38 37 5 7 Pin Name IN0, /IN0 IN1,/IN1 IN2,/IN IN3,/IN3 VT0 VT1 VT2 VT3 SIN0 SIN1 SOUT0 SOUT1 CONFIG LOAD Pin Function Differential Inputs: These input pairs are the differential signal inputs to the device. They accept differential signals as small as 100mV (200mVPP). Each input pin internally terminates with 50 to the VT pin. Note that these inputs will default to an indeterminate state if left open. Please refer to the "Interface Applications" section for more details. Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. This pin provides a center-tap to a termination network for maximum interface flexibility. An internal high impedance resistor divider biases VT to allow input AC-coupling. For AC-coupling, bypass VT with a 0.1F low ESR capacitor to VCC. See "Interface Applications" subsection and Figure 2a. These single-ended TTL/CMOS-compatible inputs address the data inputs during switch configuration. Note that this input is internally connected to a 25k ohm pullup resistor and will default to a logic HIGH state if left open. These single-ended TTL/CMOS-compatible inputs address the data outputs during switch configuration. Note that these inputs are internally connected to a 25k pullup resistor and will default to logic HIGH state if left open. These single-ended TTL/CMOS-compatible inputs control the transfer of the addresses defined by SIN0/1 and SOUT0/1. See "Switch Configuration," "Address Table" and "Timing Diagram" sections for more details. Note that these inputs are internally connected to a 25k pull-up resistor and will default to logic HIGH state if left open. 1. Load: Loads configurations into first set of latches. After programming SIN and SOUT with input and output address respectively, pulse the LOAD signal with a Low to High to Low signal to latch SIN and SOUT. Four LOAD pulses are needed, each LOAD pulse for each output. See simplified control circuit and switch configuration description on page 9 for further clarification. 2. CONFIG: Loads new configuration into the second set of latches and updates switch configuration. After Loading, pulse CONFIG with a Low to High to Low signal to load/transfer the latched signal to the output. See simplified control circuit and switch configuration description on Page 9 for further clarification. If the LOAD and CONFIG control signals are floating, one of the output pairs is set by the programmed SIN and SOUT addresses, as shown in address tables. For the remaining outputs, setup is random at power up or from previous programmed states. CML Differential Output Pairs: Differential buffered copy of the selected input signal. The output swing is typically 390mV. See "Interface Application" subsection for termination information.
23,24 26,27 29,30 32,33 6 22,25,28,31,34 12,13,20,21,35, 36,43,44 1,11,14,42
Q0, /Q0 Q1, /Q1 Q2, /Q2 Q3, /Q3 VCC VCCO GND, Exposed pad NC
Positive Power Supply: Bypass with 0.1uF//0.01uF low ESR capacitors as close to the VCC pin as possible. Supplies input and core circuitry. Output Supply: Bypass with 0.1uF//0.01uF low ESR capacitors as close to the VCCO pins as possible. Supplies the output buffer. Ground: Exposed pad must be connected to a ground plane that is at the same potential as the ground pin. Not Connected.
September 2008
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SY56040AR
Absolute Maximum Ratings(1)
Supply Voltage (VCC) ............................... -0.5V to +3.0V Supply Voltage (VCCO) ............................. -0.5V to +2.7V VCC - VCCO .........................................................<1.8V VCCO - VCC .........................................................<0.5V Input Voltage (VIN) ............................-0.5V to VCC + 0.5V CML Output Voltage (VOUT) ................0.6V to VCCO+0.5V Current (VT) Source or sink current on VT pin .................100mA Input Current Source or sink current on (IN, /IN) .................50mA Maximum Operating Junction Temperature.......... 125C Lead Temperature (soldering, 20sec.) .................. 260C Storage Temperature (Ts) ....................-65C to +150C
Operating Ratings(2)
Supply Voltage (VCC) ......................... 2.375V to 2.625V (VCCO).............................................. 1.14V to 2.625V Ambient Temperature (TA).................... -40C to +85C (3) Package Thermal Resistance (R) MLF Still-air (JA) ............................................40C/W Junction-to-board (JB) .........................20C/W
DC Electrical Characteristics(4)
TA = -40C to +85C, unless otherwise stated.
Symbol VCC Parameter Power Supply Voltage Range Condition VCC VCCO VCCO VCCO Max. VCC No Load. Max. VCCO 45 90 IN, /IN VIL with VIHMIN = 1.2V IN, /IN VIL with VIHMIN = 1.14V (1.2V-5%) see Figure 3a see Figure 3b 1.2 0.2 1.14 0.66 0.1 0.2 Min 2.375 1.14 1.7 2.375 Typ 2.5 1.2 1.8 2.5 155 64 50 100 Max 2.625 1.26 1.9 2.625 200 84 55 110 VCC VIH-0.1 VCC VIH-0.1 1.0 2.0 1.28 Units V V V V mA mA V V V V V V V
ICC ICCO RIN RDIFF_IN VIH VIL VIH VIL VIN VDIFF_IN VT_IN
Notes:
Power Supply Current Power Supply Current Input Resistance (IN-to-VT, /IN-to-VT ) Differential Input Resistance (IN-to-/IN) Input HIGH Voltage (IN, /IN) Input LOW Voltage (IN, /IN) Input HIGH Voltage (IN, /IN) Input LOW Voltage (IN, /IN) Input Voltage Swing (IN, /IN) Differential Input Voltage Swing (|IN - /IN|) Voltage from Input to VT
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. JB and JA values are determined for a 4-layer board in still-air number, unless otherwise stated. 4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
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SY56040AR
CML Outputs DC Electrical Characteristics(5)
VCCO = 1.14V to 1.26V, RL = 50 to VCCO, VCCO = 1.7V to 1.9V; 2.375V to 2.625V, RL = 50 to VCCO or 100 across the outputs. VCC = 2.375V to 2.625V. TA = -40C to +85C, unless otherwise stated.
Symbol VOH VOUT VDIFF_OUT ROUT Parameter Output HIGH Voltage Output Voltage Swing Differential Output Voltage Swing Output Source Impedance Condition RL = 50 to VCCO See Figure 3a See Figure 3b Min VCCO-0.020 300 600 45 Typ VCCO-0.010 390 780 50 Max VCCO 475 950 55 Units V mV mV
LVTTL/CMOS DC Electrical Characteristics(5)
VCC = 2.5V 5%. TA = -40C to +85C, unless otherwise stated.
Symbol VIH VIL IIH IIL
Note: 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current
Condition
Min 2.0 -125 -300
Typ
Max VCC 0.8 30
Units V V A A
September 2008
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Micrel, Inc.
SY56040AR
AC Electrical Characteristics(6)
VCCO = 1.14V to 1.26V, RL = 50 to VCCO, VCCO = 1.7V to 1.9V, 2.375V to 2.625V, RL = 50 to VCCO or 100 across the outputs. VCC = 2.375V to 2.625V. TA = -40C to +85C, unless otherwise stated.
Symbol fMAX tPD Parameter Maximum Data Rate/ Frequency Propagation Delay IN-to-Q CONFIG-to-Q LOAD/CONFIG-Q Condition NRZ Data VOUT > 200mV Clock Min 6.4 5 200 290 450 850 1500 Note 7, Fig. 1b, Fig. 1c 600 600 800 800 1400 300 800 500 600 500 25 12 50 25 75 1 10 1 10 0.7 20 47 45 50 80 53 55 ps ps 400 Typ Max Units Gbps GHz ps ps
tPW tS
Pulse Width of LOAD/CONFIGIG signal Set-up Time SIN-to-LOAD SIN-to-LOAD/CONFIG SOUT-to-LOAD SOUT-to-LOAD/CONFIG LOAD-to-CONFIG CONFIG-to-LOAD LOAD-to-SIN LOAD/CONFIG-to-SIN LOAD-to-SOUT LOAD/CONFIG-to-SOUT
tH
Hold time
Note 8, Fig. 1b, Fig. 1c
ps
tSkew
Input-to-Input skew Output-to-Output skew Part-to-Part Skew
Note 9 Note 10 Note 11 Random Jitter Deterministic Jitter Cycle-to-Cycle Jitter Total Jitter Crosstalk Induced Jitter (Adjacent Channel) Note 12 Note 13 Note 14 Note 15 Note 16 At full output swing. Differential I/O 4GHz Differential I/O 5GHz
ps ps ps psRMS psPP psRMS psPP psPP ps % %
tJitter
Data Clock
tR, tF
Output Rise/Fall Times (20% to 80%) Duty Cycle
Notes: 6. High frequency AC electrical values are guaranteed by design and characterization. 7. Set-up time is the time a signal has to be present before the rising edge of the clock /control signal comes by. For example, tS (SIN-LOAD/CONFIG), requires the time SIN has to transition before the L-H edge of the LOAD/CONFIG signal asserts. 8. Hold time is the time a signal has to be present after the falling edge of the clock edge/control signal comes by. For example, tH (LOAD/CONFIG-SIN) defines the time SIN signal has to transition after the H-L edge of the LOAD/CONFIG signal asserts. 9. Input-to-Input skew is the difference in time between 4 inputs, measured at the same output, for the same temperature, voltage, and transition. 10. Output-to-Output skew is the difference in time between 4 outputs, receiving data from the same input, for the same temperature, voltage and transition. 11. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the respective inputs. 12. Random jitter is measured with a K28.7 pattern, measured at fMAX. 13. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 223-1 PRBS pattern. 14. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. tJITTER_CC = Tn -Tn+1, where T is the time between rising edges of the output signal. 15. Total jitter definition: with an ideal clock input frequency of fMAX (device), no more than one output edge in 1012 output edges will deviate by more than the specified peak-to-peak jitter value. 16. Crosstalk induced jitter is defined as the added jitter that results from signals applied to the adjacent channel. It is measured at the output. While applying a similar, differential clock frequency to both inputs that is asynchronous with respect to each other.
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SY56040AR
Switch Configuration
As shown in the Simplified Control Circuit below, Figure 1a, each output channel consists of two sets of latches. The first set of latches stores the SIN information for each SOUT selected. The second set of latches transfers this stored information to the output MUX circuitry. These latches are transparent when EN is high and latched when EN is low. Two pins, LOAD and CONFIG, control the programming. LOAD is ANDed with the SOUT pins to route the SIN data to the appropriate first set of latches. CONFIG subsequently transfers the information in the first set of latches to the second set of latches, which is connected to the output MUX circuitry. There are two ways to program this device. The first is a Dual Control Mode, as shown in Figure 1b. First, all the input-output (SIN-SOUT) information is loaded. Second, this information is transferred to the output control circuitry. Each LOAD pulse loads the input information (SIN) to be assigned to the output (SOUT). In maximum, four LOAD pulses are applied, one LOAD pulse for each output. Note that LOAD pulses are necessary only for undefined and/or modified input-output combinations. After all the input-output information is loaded, the CONFIG is pulsed to transfer and latch this information to the output control circuitry. The second programming method is the Single Control Mode, shown in Figure 1c, in which LOAD and CONFIG are tied together. Each individual output receives the appropriate input information in a oneshot control pulse. When one output is being programmed, the other outputs remain unaffected until its turn occurs.
Interface Applications
For Input Interface Applications, see Figures 4a through 4f. For CML Output Termination, see Figures 5a through Figure 5d. CML Output Termination with VCCO 1.2V For VCCO of 1.2V, Figure 5a, terminate the output with 50 to1.2V, DC-coupled, not 100 differentially across the outputs. If AC-coupling is used, Figure 5d, terminate into 50to-1.2V before the coupling capacitor and then connect to a high value resistor to a reference voltage. Do not AC-couple with internally terminated receiver, such as 50 ANY-IN input. AC-coupling will offset the output voltage by 200mV and this offset voltage will be too low for proper driver operation. Any unused output pair needs to be terminated when VCCO is 1.2V, do not leave floating. CML Output Termination with VCCO 1.8V, 2.5V For VCCO of 1.8V and 2.5V, refer to Figure 5a and Figure 5b, terminate with either 50 to VCCO or 100 differentially across the outputs. See Figure 5c for AC-coupling. Input AC-Coupling The SY56040AR input can accept AC-coupling from any driver. Bypass VT with a 0.1F low ESR capacitor to VCC as shown in Figures 4c and 4d. VT has an internal high impedance resistor divider as shown in Figure 2a, to provide a bias voltage for AC-coupling.
Figure 1a. Simplified Control Circuit
September 2008
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SY56040AR
Timing Diagrams
Figure 1b. Dual-Control Mode Timing Diagram
Figure 1c. Single-Control Mode Timing Diagram Note 17. Invalid and valid refer to configurations being changed. All outputs with unchanged configurations remain valid.
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SY56040AR
Typical Characteristics
VCC = 2.5V, VCCO =1.2V, GND = 0V, VIN = 100mV, RL = 50 to 1.2V, TA = 25C, unless otherwise stated.
Functional Characteristics
VCC = 2.5V, VCCO = 2.5V, GND = 0V, VIN = 100mV, RL = 50 to 2.5V, Data Pattern: 2 -1, TA = 25C, unless otherwise stated.
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SY56040AR
Input and Output Stage
Figure 2a. Simplified Differential Input Buffer
Figure 2b. Simplified CML Output Buffer
Single-Ended and Differential Swings
Figure 3a. Single-Ended Swing
Figure 3b. Differential Swing
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SY56040AR
Input Interface Applications
Figure 4a. CML Interface (DC-Coupled, 1.8V, 2.5V) Option: May connect VT to VCC
Figure 4b. CML Interface (DC-Coupled, 1.2V)
Figure 4c. CML Interface (AC-Coupled)
Figure 4d. LVPECL Interface (AC-Coupled)
Figure 4e. LVPECL Interface (DC-Coupled)
Figure 4f. LVDS Interface
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SY56040AR
CML Output Termination
Figure 5a. 1.2V, 1.8V or 2.5V CML DC-Coupled Termination
Figure 5b. 1.8V or 2.5V CML DC-Coupled Termination
Figure 5c. CML AC-Coupled Termination (VCCO 1.8V or 2.5V)
Figure 5d. CML AC-Coupled Termination (VCCO 1.2V only)
Related Product and Support Documents
Part Number HBW Solutions SY58040U SY89540U Function New Products and Termination Application Notes 4x4 CML switch with internal I/O term. 4x4 LVDS switch with internal I/O term. Datasheet Link http://www.micrel.com/page.do?page=/productinfo/as/HBWsolutions.shtml http://www.micrel.com/_PDF/HBW/sy58040u.pdf#page=3 http://www.micrel.com/_PDF/HBW/sy89540u.pdf#page=3
September 2008
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Micrel, Inc.
SY56040AR
Package Information
44-Pin MicroLeadFrame (MLF-44)
(R)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2008 Micrel, Incorporated.
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